Increasing requirements for ESD protective breathing innovative architecture Strategies

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  The higher data rates through the new I / O, such as HDMI, SATA, DisplayPort, MIPI and engineers are needed studying ways to reduce the ability of electrostatic discharge (ESD) protection devices. Manufacturer, but are willing to a higher level through finer process geometries offer are vulnerable to attack by EDS.
  
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  EDS is now struggling with traditional architectures to ensure adequate protection and support the desired speeds, the design community before a big dilemma. As a result, engineers are forced to difficult trade-offs between reliability and quality of the signal, which threatens an element of the overall system performance. Chip design that can meet the new demands for both higher throughput and better ESD protection has become a difficult task for manufacturers.
  
  The development of the ESD protection
  
  The landscape of the ESD protection has undergone a dramatic change with the acquisition of producing smaller geometries, the lined and the protection of the changing environment of the application:
  
  Small geometries: What process node semiconductors for advanced nowadays integrated circuits (ASICs) and 90 nm fell below the level of voltage and power outages occur that discharge also produce lower. Interfaces widespread adoption of high-speed data increases the complexity of maintaining signal integrity and maintaining an adequate level of ESD protection. Robust ESD protection usually means higher capacity, which threaten to adversely affect the signal-to-noise ratio (SNR), forcing developers to one or the other.
  
  Reduces chip protection: ESD damage sensitivity was well known. For example, the Industry Council on ESD Targets recently announced an initiative to reduce the level of standard on-chip ESD protection, so that the external ESD protection circuits against the more critical for system reliability.
  
  Changes in the application environment: laptops, cell phones, MP3 players, digital cameras and other portable consumer devices to be used in uncontrolled environments (ie, without the use of adhesive tape to the ground strap or polished driver / tops). In these environments, user I / O connector pins when connecting / disconnecting cables. Portable device also charge can accumulate during normal use and then discharged when power to another device, such as for example, connected to a computer or a television.
  
  Equalization impedance
  
  A matched impedance of the total transmission line is a critical factor in the drawings, a high speed. The characteristic impedance is affected by many factors, including the line width, the thickness of the dielectric plate, sheet materials, and components of the traces.
  
  The characteristic impedance of a transmission line is the square root of L / C, where L is the inductance and C is the capacitance, the. Therefore, if the additional capacity to a point, then the impedance is reduced at this point. Conversely, when the inductance is added to increase the impedance. The inclusion of an ESD protection circuit is due to its own ability to influence the impedance of the line. Consequently, it must be compensated by an impedance matching.
  
  Although the main goal of an optimized design matches the impedance of the line, is entitled to 100 Ω ± 15% in the HDMI standard. Each guard added to. The line when a diode varistor suppressor or polymer inserts, the ability to not only from the device itself, but also the connection points of the printed circuit board unit (PCB)
  
  Increased capacity and distorts the signal of poor quality video and even failure of the compliance test result. Therefore, the ESD protection vendors have concentrated on reducing the capacity of their plants. However, as already mentioned, this negative impact on the performance of the ESD protection. For example, the capacitance of the diode can be reduced by reducing its size. This may lead to increase the resistance, but this will result in a higher voltage and leakage current terminal to reach the protected device.
  
  Compensation techniques
  
  In order to compensate for the additional protection device performance, system designers often try to reduce the capacity elsewhere on the board, or add an additional inductance. Compensation techniques typically include:
  
  • Adding a common mode choke or filter: The inductance of a coil can compensate additional capacity ESD device. Unfortunately, the high speed Common Mode Inductors design can be very costly and should be avoided.
  
  • Reducing the width of the track in the protection (increased inductance trace): Often referred to as "trace necking", this technique can be very effective if only small amounts of compensation are required, however, a restriction thin dielectric. occurs and the capacity of the ESD protection device is too high, it may be difficult to achieve a suitable impedance.
  
  • Reduce trace capacitance: This can by removing the lower ground plane and reduce the possibility of plot done in the field of ESD.
  
  Although each of these techniques has been successful at best suboptimal due to the additional complexity of the design and cost. You need good design and control of manufacturing processes and environments, the use of expensive external components (such as common mode chokes) or complex PCBs increased total bill. Another drawback is that many engineers do not have enough experience in the design of controlled impedance layout. This lack of experience often leads to errors in design and development costs and snowballs as schedule multiple grafts and checkerboard design and production. Finally, many large manufacturers favor with several suppliers of PCBs that make it difficult to handle a unique design that makes making works with all providers.
  
  A new approach
  
  Given the significant shortcomings of these compensatory techniques to investigate further semiconductor manufacturers for innovative architectures to ensure the integrity, even at high data rates required by the industry today. And they do this without the possibility of ESD protection element is of paramount importance in doubt.
  
  One example is the architecture PicoGuard XS. According to the developers, ON Semiconductor, the integrity of the interface data signals defend at a high speed while improving the ESD protection. This eliminates the parasites, routing and tracking on the package, instead of the bottom. We reject any compensation from the integration of external inductors with the ESD diode, corresponding to the impedance of the signal line. Inductors integrated ESD to improve performance by reducing the voltage and residual current seen blocking the ASIC.
  
  Standard packaging structure allows the soil around the lower part of the body (Fig. 1). That is, the wire bond pads of the die is still very long, which. An adjustment of the inductance So the motherboard manufacturer does not need to make a compensation method. In addition, with respect to the dynamic resistance (RDYN) surpass using product architecture PicoGuard XS other traditional flow through parts that says protecting high speed differential data lines ON Semiconductor.
  
  The architecture eliminates the need to change or inductances wide traces on the board. Also not on the stacked card, the system designer with multiple providers, configure without an impedance table for each supplier to make depend. Capable of an impedance is independent of the number of layers of the circuit board game, the thickness of the dielectric, and other variables provide specific design.
  
  Here Comes The Science Bit
  
  ESD protection device for an inductor standard provides the parasitic inductance of the wire and the conductor paths leading to the protective device (Figure 2). The inductive element has a high impedance high impact ESD download speed, which limits the ability of the guard to quickly absorb energy. As a result, more energy reaches the protected ASIC.
  
  In contrast, the inductive elements of the architecture PicoGuard XS series with the conduction path for the protection ASIC (Fig. 3). What actually limiting current and voltage of the device deprotection. Firstly, the inductive reactance is L1 connector holding an electrostatic discharge. It acts in the opposite direction of the current ESD, helps to limit the peak voltage type. The inductive reactance in L2 firepower pull side ASIC ESD current limited then by ESD protection diodes. The same time the voltage drop across the two elements in series to reduce the voltage in the ASIC parameters as protected.
  
  Completion
  
  The next generation of electronic devices that support data transfer marry at high speed with high signal integrity and chain of custody of electrostatic discharge. This requires a fundamental change in the design of ESD protection, because now is the point where the borders of traditional techniques capacitance compensation are too large, achieved. It was the advent of advanced architectures, requires the signal integrity for high-speed interfaces and provides ESD protection required for reliable operation possible.
  
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